1. Field of the Invention
This invention relates to a semiconductor memory device and more particularly to a semiconductor memory device including floating body cells (FBCs) each of which dynamically stores data with the channel body of a transistor used as a storage node.
2. Description of the Related Art
Conventionally, a general dynamic random access memory (DRAM) which is used as a memory with high integration density contains memory cells each of which is configured by one metal oxide semiconductor (MOS) transistor and one capacitor. Further, for example, an static random access memory (SRAM) contains memory cells each of which is configured by four or six MOS transistors. Thus, since the number of constituents and the cell area of the DRAM are smaller than those of the SRAM, the DRAM is widely used as a memory with high integration density. However, in order to acquire a capacitor of preset capacitance or more (several fF to several ten fF) used to store data in a limited cell area, a complicated capacitor structure of a so-called stack type or trench type is required, for example. Further, it is expected that the structure is miniaturized in future, the capacitor structure and manufacturing process become unavoidably complicated, and therefore, a problem that the manufacturing yield is lowered and the manufacturing cost rises will occur.
Therefore, a new memory which makes the capacitor required in the DRAM cell unnecessary is proposed. As the new memory which makes the capacitor unnecessary, a floating body cell (FBC) which dynamically stores data with the channel body of a transistor used as a storage node is provided. For example, one example of the array structure and the cross-sectional view of a memory cell of the FBC is shown in FIGS. 19A to 19N in Jpn. Pat. Appln. KOKAI Publication No. 2002-343886. That is, each memory cell of the FBC has one MOS transistor with the channel body used as a storage node as the basic configuration of a memory cell.
However, in the conventional semiconductor memory device disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2002-343886 and the like, the design thereof becomes unreasonable in order to attain a cell area of 4F2 (F is determined by a design rule). More specifically, for example, since the source and drain are commonly used by adjacent cells, carriers are transferred between the channel bodies of the adjacent cells if the diffusion length of carriers (which are carriers stored in the channel body and correspond to minority carriers in the source and drain diffusion layers) in the source and drain diffusion layers becomes longer than that defined by the design rule. As a result, there occurs a possibility that data disturbance (information destruction) occurs. Further, since the high-impurity concentration layer of part of the channel body portion lies adjacent to the source and drain, the junction leak current increases and the retention characteristic may be deteriorated.